Computer systems typically employ one or more interconnects to facilitate communication between system components, such as between processors and memory. Interconnects and/or expansion interfaces may also be used to support built-in and add on devices, such as IO (input/output) devices and expansion cards and the like. For many years after the personal computer was introduced, the primary form of interconnect was a parallel bus. Parallel bus structures were used for both internal data transfers and expansion buses, such as ISA (Industry Standard Architecture), MCA (Micro Channel Architecture), EISA (Extended Industry Standard Architecture) and VESA Local Bus. In the early 1990's Intel Corporation introduced the PCI (Peripheral Component Interconnect) computer bus. PCI improved on earlier bus technologies by not only increasing the bus speed, but also introducing automatic configuration and transaction-based data transfers using shared address and data lines.
As time progressed, computer processor clock rates where increasing at a faster pace than parallel bus clock rates. As a result, computer workloads were often limited by interconnect bottlenecks rather than processor speed. Although parallel buses support the transfer of a large amount of data (e.g., 32 or even 64 bits under PCI-X) with each cycle, their clock rates are limited by timing skew considerations, leading to a practical limit to maximum bus speed. To overcome this problem, high-speed serial interconnects were developed. Examples of early serial interconnects include Serial ATA, USB (Universal Serial Bus), FireWire, and RapidIO.
Another standard serial interconnect that is widely used is PCI Express, also called PCIe, which was introduced in 2004 under the PCIe 1.0 standard. PCIe was designed to replace older PCI and PCI-X standards, while providing legacy support. PCIe employs point-to-point serial links rather than a shared parallel bus architecture. Each link supports a point-to-point communication channel between two PCIe ports using one or more lanes, with each lane comprising a bi-directional serial link. The lanes are physically routed using a crossbar switch architecture, which supports communication between multiple devices at the same time. As a result of its inherent advantages, PCIe has replaced PCI as the most prevalent interconnect in today's personal computers. PCIe is an industry standard managed by the PCI-SIG (Special Interest Group). As such, PCIe pads are available from many ASIC and silicon vendors.
Processors and memory continue on a course in accordance with Moore's law, albeit recent processor speed increases are based primarily on having multiple cores rather than on increases in clock rate. However, the rate of interconnect speeds, particularly for serial links such as PCIe, have not been able to keep up. This is due in part to finite limits on clock rates in view of current technologies. Accordingly, rather than focus on increasing speed based on higher clock rates, other schemes have been recently introduced or proposed. For example, the PCIe 3.0 specification doubles the PCIe 2.x interconnect bandwidth by using a combination of increased clock rate and switching to 8 bit encoding from PCIe's standard 8 b/10 b encoding (10 bits of encoded data for every 8 bits of usable data).
Another approach for increasing effective link bandwidth is using data compression. There are several viable data compression schemes used for various types of data transfers. However, the overhead and computational requirements associated with many of these schemes make them impractical for use in high-speed serial interconnects such as PCIe. For example, in order to be beneficial the average speed improvement gain must be greater than the average overhead increase due to the compression/decompression operations (in terms of transfer latency). Since the PCIe protocol payload size limit is only 4 KB (and most packet payloads for actual implementations are typically limited to 256 bytes (for server chipsets) and 128 bytes (for client chipsets)), there is generally no benefit (and, in fact there would typically be a detriment) if conventional compression encoding techniques were to be employed on a PCIe link. Accordingly, it would be advantageous to implement a high-bandwidth lossless compression/decompression scheme for high-speed interconnects with no or minimal transfer latency due to processing overhead.